Design for Debug: Catching Design Errors in Digital Chips
IEEE Design & Test
Core-Based Scan Architecture for Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
An event-based monitoring service for networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Transaction-Based Communication-Centric Debug
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A multi-core debug platform for NoC-based systems
Proceedings of the conference on Design, automation and test in Europe
In-band cross-trigger event transmission for transaction-based debug
Proceedings of the conference on Design, automation and test in Europe
Transaction-based debugging of system-on-chips with patterns
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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Existing SoC debug techniques mainly target bus-based systems. They are not readily applicable to the emerging system that use Network-on-Chip (NoC) as on-chip communication scheme. In this paper, we present the detailed design of a novel debug probe (DP) inserted between the core under debug (CUD) and the NoC. With embedded configurable triggers, delay control and timestamping mechanism, the proposed DP is very effective for inter-core transaction analysis as well as controlling embedded cores' debug processes. Experimental results show the functionalities of the proposed DP and its area overhead1.