Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
The turn model for adaptive routing
Journal of the ACM (JACM)
Distributed, Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
A quantitative comparison of parallel computation models
ACM Transactions on Computer Systems (TOCS)
A bandwidth-efficient architecture for media processing
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 37th Annual Design Automation Conference
Smart Memories: a modular reconfigurable architecture
Proceedings of the 27th annual international symposium on Computer architecture
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Contention-free communication scheduling for array redistribution
Parallel Computing
On the benefit of supporting virtual channels in wormhole routers
Journal of Computer and System Sciences
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Encodings for high-performance for energy-efficient signaling
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Powering networks on chips: energy-efficient and reliable interconnect design for SoCs
Proceedings of the 14th international symposium on Systems synthesis
A General Theory for Deadlock-Free Adaptive Routing Using a Mixed Set of Resources
IEEE Transactions on Parallel and Distributed Systems
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Future directions in clocking multi-ghz systems
Proceedings of the 2002 international symposium on Low power electronics and design
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
A Delay Model for Router Microarchitectures
IEEE Micro
Impact of Virtual Channels and Adaptive Routing on Application Performance
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels
IEEE Transactions on Parallel and Distributed Systems
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Hierarchical Interconnects for On-Chip Clustering
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Networks on Silicon: Blessing or Nightmare?
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
aSOC: A Scalable, Single-Chip Communications Architecture
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Interfacing Cores with On-chip Packet-Switched Networks
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Managing Power Consumption in Networks on Chip
Proceedings of the conference on Design, automation and test in Europe
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Networks on chip
Clocking strategies for networks-on-chip
Networks on chip
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Network-on-Chip Modeling for System-Level Multiprocessor Simulation
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Topology optimization for application-specific networks-on-chip
Proceedings of the 2004 international workshop on System level interconnect prediction
Proceedings of the conference on Design, automation and test in Europe - Volume 1
How Can System-Level Design Solve the Interconnect Technology Scaling Problem?
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Case Study in Networks-on-Chip Design for Embedded Video
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Interconnect intellectual property for network-on-chip (NoC)
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Micro-Network for SoC: Implementation of a 32-Port SPIN network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An architecture and compiler for scalable on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
An Asynchronous Router for Multiple Service Levels Networks on Chip
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Issues in the development of a practical NoC: the Proteo concept
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality
MASCOTS '05 Proceedings of the 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
Application-specific buffer space allocation for networks-on-chip router design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
MAIA: a framework for networks on chip generation and verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
A global wiring paradigm for deep submicron design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A survey and comparison of wormhole routing techniques in a mesh networks
IEEE Network: The Magazine of Global Internetworking
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Converting massive TLP to DLP: a special-purpose processor for molecular orbital computations
Proceedings of the 4th international conference on Computing frontiers
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures
Journal of Systems Architecture: the EUROMICRO Journal
Architecture of the Scalable Communications Core
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Implementing DSP Algorithms with On-Chip Networks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method
Proceedings of the conference on Design, automation and test in Europe
A multi-core debug platform for NoC-based systems
Proceedings of the conference on Design, automation and test in Europe
Fitting the router characteristics in NoCs to meet QoS requirements
Proceedings of the 20th annual conference on Integrated circuits and systems design
Router architecture for high-performance NoCs
Proceedings of the 20th annual conference on Integrated circuits and systems design
JTRES '07 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems
Using metro-on-chip in physical design flow for congestion and routability improvement
Microelectronics Journal
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
VEBoC: variation and error-aware design for billions of devices on a chip
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 18th ACM Great Lakes symposium on VLSI
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Nanonetworks: A new communication paradigm
Computer Networks: The International Journal of Computer and Telecommunications Networking
PowerAntz: distributed power sharing strategy for network on chip
Proceedings of the 13th international symposium on Low power electronics and design
Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Re-examining the use of network-on-chip as test access mechanism
Proceedings of the conference on Design, automation and test in Europe
A simplified executable model to evaluate latency and throughput of networks-on-chip
Proceedings of the 21st annual symposium on Integrated circuits and system design
Modeling and Implementation of an Output-Queuing Router for Networks-on-Chips
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Heuristics Core Mapping in On-Chip Networks for Parallel Stream-Based Applications
ICCS '08 Proceedings of the 8th international conference on Computational Science, Part I
A Hardware-Software Design Framework for Distributed Cellular Computing
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Relieving physical issues in new NoC-based SoCs
Proceedings of the 2nd international conference on Nano-Networks
Engineering of Software-Intensive Systems: State of the Art and Research Challenges
Software-Intensive Systems and New Computing Paradigms
Long-range dependence and on-chip processor traffic
Microprocessors & Microsystems
In-Network Caching for Chip Multiprocessors
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Analysis of communication delay bounds for network on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Off-chip communication architectures for high throughput network processors
Computer Communications
Multicast routing with dynamic packet fragmentation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
Microprocessors & Microsystems
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Proceedings of the 23rd international conference on Supercomputing
Application-aware deadlock-free oblivious routing
Proceedings of the 36th annual international symposium on Computer architecture
Lossless and Near-Lossless Image Compression Scheme Utilizing Blending-Prediction-Based Approach
ICCVG 2008 Proceedings of the International Conference on Computer Vision and Graphics: Revised Papers
Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Microprocessors & Microsystems
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Applying network calculus for performance analysis of self-similar traffic in on-chip networks
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Vicis: a reliable network for unreliable silicon
Proceedings of the 46th Annual Design Automation Conference
Model Based Testing of a Network-on-Chip Component
Electronic Notes in Theoretical Computer Science (ENTCS)
Breaking adaptive multicast deadlock by virtual channel address/data FIFO decoupling
Proceedings of the 2nd International Workshop on Network on Chip Architectures
A networks-on-chip architecture design space exploration - The LIB
Computers and Electrical Engineering
A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures
Computers and Electrical Engineering
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
A system-level design methodology for application-specific networks-on-chip
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Design Trade-offs in Customized On-chip Crossbar Schedulers
Journal of Signal Processing Systems
An accurate and efficient performance analysis approach based on queuing model for Network on Chip
Proceedings of the 2009 International Conference on Computer-Aided Design
Throughput-oriented NoC topology generation and analysis for high performance SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An analysis of on-chip interconnection networks for large-scale chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Journal of Signal Processing Systems
Statistical estimation and evaluation for communication mapping in Network-on-Chip
Integration, the VLSI Journal
Partially reconfigurable point-to-point interconnects in Virtex-II pro FPGAs
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Systematic customization of on-chip crossbar interconnects
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
A modeling tool for simulating and design of on-chip network systems
Microprocessors & Microsystems
rHALB: a new load-balanced routing algorithm for k-ary n-cube networks
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
A flexible parallel simulator for networks-on-chip with error control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Fault tolerant network on chip switching with graceful performance degradation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
An efficient dynamically reconfigurable on-chip network architecture
Proceedings of the 47th Design Automation Conference
PowerAntz: Ant behavior inspired power budget distribution scheme for Network-on-Chip systems
Microelectronics Journal
Quarter Load Threshold (QLT) flow control for wormhole switching in mesh-based Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
Flexible interconnection network for dynamically and partially reconfigurable architectures
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
An overview of achieving energy efficiency in on-chip networks
International Journal of Communication Networks and Distributed Systems
Next generation on-chip networks: what kind of congestion control do we need?
Hotnets-IX Proceedings of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks
Proceedings of the Conference on Design, Automation and Test in Europe
A highly resilient routing algorithm for fault-tolerant NoCs
Proceedings of the Conference on Design, Automation and Test in Europe
A monitor interconnect and support subsystem for multicore processors
Proceedings of the Conference on Design, Automation and Test in Europe
Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
State observer controller design for packets flow control in networks-on-chip
The Journal of Supercomputing
Area and power-efficient innovative congestion-aware Network-on-Chip architecture
Journal of Systems Architecture: the EUROMICRO Journal
Network-on-Chip interconnect for pairing-based cryptographic IP cores
Journal of Systems Architecture: the EUROMICRO Journal
A unified design space simulation environment for network-on-chip: fuse-N
International Journal of High Performance Systems Architecture
A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip
Microprocessors & Microsystems
Hierarchical circuit-switched NoC for multicore video processing
Microprocessors & Microsystems
System design of full HD MVC decoding on mesh-based multicore NoCs
Microprocessors & Microsystems
Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture
Microprocessors & Microsystems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
On the design and analysis of fault tolerant NoC architecture using spare routers
Proceedings of the 16th Asia and South Pacific Design Automation Conference
3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms
Journal of Parallel and Distributed Computing
An improvement of router throughput for on-chip networks using on-the-fly virtual channel allocation
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Modified bundled-data as a new protocol for NoC asynchronous links
Microelectronics Journal
An ROBDD-based combinatorial method for the evaluation of yield of defect-tolerant systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3D floorplanning of low-power and area-efficient Network-on-Chip architecture
Microprocessors & Microsystems
A distributed and topology-agnostic approach for on-line NoC testing
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs
Proceedings of the 24th symposium on Integrated circuits and systems design
Virtual path implementation of multi-stream routing in network on chip
PaCT'11 Proceedings of the 11th international conference on Parallel computing technologies
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
BOFAR: buffer occupancy factor based adaptive router for mesh NoCs
Proceedings of the 4th International Workshop on Network on Chip Architectures
Stochastic communication for application-specific Networks-on-Chip
The Journal of Supercomputing
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Network-on-Chip routing algorithms by breaking cycles
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
A generic packet router IP for multi-processors network-on-chip
Proceedings of the 8th FPGAWorld Conference
Streamlined network-on-chip for multicore embedded architectures
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Benefits of selective packet discard in networks-on-chip
ACM Transactions on Architecture and Code Optimization (TACO)
A novel 3D NoC architecture based on De Bruijn graph
Computers and Electrical Engineering
R-NoC: an efficient packet-switched reconfigurable networks-on-chip
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
Formal verification methodology considerations for network on chips
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
System-level application-specific NoC design for network and multimedia applications
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Power consumption and performance analysis of 3D NoCs
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Design and analysis of multicast communication in multidimensional mesh networks
ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications
Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
Journal of Computer and System Sciences
Efficient genetic based topological mapping using analytical models for on-chip networks
Journal of Computer and System Sciences
Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints
ACM Transactions on Architecture and Code Optimization (TACO)
Hamiltonian properties of honeycomb meshes
Information Sciences: an International Journal
Test pin count reduction for NoC-based test delivery in multicore SOCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
An energy-aware online task mapping algorithm in NoC-based system
The Journal of Supercomputing
A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
ACM Transactions on Embedded Computing Systems (TECS)
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
User satisfaction aware routing decisions in NOC
Proceedings of the Sixth International Workshop on Network on Chip Architectures
An analytical model for on-chip interconnects in multimedia embedded systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
Asymmetric scaling on network packet processors in the dark silicon era
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faults
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture
Wireless Personal Communications: An International Journal
Energy and buffer aware application mapping for networks-on-chip with self similar traffic
Journal of Systems Architecture: the EUROMICRO Journal
Integration, the VLSI Journal
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes
Microprocessors & Microsystems
Non-minimal, turn-model based NoC routing
Microprocessors & Microsystems
Microprocessors & Microsystems
X-Network: An area-efficient and high-performance on-chip wormhole interconnect network
Microprocessors & Microsystems
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The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.