A system-level design methodology for application-specific networks-on-chip

Authors:
Alexandros Bartzas;Lazaros Papadopoulos;Dimitrios Soudris
Affiliations:
(Correspd. E-mail: ampartza@ee.duth.gr) VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100, Xanthi, Greece;VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100, Xanthi, Greece;Microprocessors and Digital Systems Lab, School of Electrical and Computer Engineering, National Technical University of Athens, 15780 Zografou, Greece
Venue:
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Year:
2009

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Abstract

Modern embedded consumer devices execute complex network and multimedia applications that require high performance and low energy consumption. For implementing complex applications on Network-on-Chips (NoCs), a design methodology is needed for performing exploration at NoC system-level, in order to select the optimal application-specific NoC architecture, serving the application requirements in the best way. The design methodology we present in this paper is based on the exploration of different NoC characteristics and is supported by a flexible NoC simulator which provides the essential evaluation metrics in order to select the optimal communication parameters of the NoC architectures. We illustrated that it is possible with the evaluation metrics provided by the simulator we present, to perform exploration of several NoC aspects and select the optimal communication characteristics for NoC platforms having network and multimedia applications as the target domains. With our methodology we can achieve a gain of 57% in the Energy × Delay Product on average.