Chain: A Delay-Insensitive Chip Area Interconnect

Authors:
John Bainbridge;Steve Furber
Affiliations:
-;-
Venue:
IEEE Micro
Year:
2002

Citing 9
Cited 57

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Abstract

The increasing complexity of system-on-a-chip designs exposes the limits imposed by the standard synchronous bus. the authors propose a mixed system as a solution.