A GALS Infrastructure for a Massively Parallel Multiprocessor

Authors:
Luis A. Plana;Steve B. Furber;Steve Temple;Mukaram Khan;Yebin Shi;Jian Wu;Shufan Yang
Affiliations:
University of Manchester;University of Manchester;University of Manchester;University of Manchester;University of Manchester;University of Manchester;University of Manchester
Venue:
IEEE Design & Test
Year:
2007

Citing 2
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Abstract

The Spinnaker (Spiking Neural Network Architecture) system for large-scale neural modeling is based on a scalable processor chip containing multiple ARM cores. Using a globally asynchronous, locally synchronous (GALS) approach allows custom, off-the-shelf IP to be readily integrated without significant timing-closure design effort. The ARM processors are used to simulate neurons, and generated neural events are carried over an on-chip, packet-switched fabric. This self-timed interconnect is also extended off chip to a provide chip-to-chip interconnect that scales to networks of thousands of chips.