Polychronization: Computation with Spikes
Neural Computation
GPUTeraSort: high performance graphics co-processor sorting for large database management
Proceedings of the 2006 ACM SIGMOD international conference on Management of data
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AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
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IEEE Design & Test
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AHS '09 Proceedings of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems
A reconfigurable architecture for emulating large-scale bio-inspired systems
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
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The performance analysis of an efficient multiprocessor architecture that allows accelerating the emulation of large-scale Spiking Neural Networks (SNNs) is reported. After describing the architecture and the complex SNN algorithm mapping, the performance study demonstrates that the system can emulate up to 10,000 300-synapse neurons in real time at 64 MHz with conventional FPGAs. Important improvements can be achieved by using advanced technology and increased clock rate or by means of simple architecture modifications. The architecture is flexible enough to be efficiently applied to any SNN model in general.