Stretching quasi delay insensitivity by means of extended isochronic forks
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Low-Latency Asynchronous FIFO's Using Token Rings
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
An Asynchronous Router for Multiple Service Levels Networks on Chip
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
A GALS Infrastructure for a Massively Parallel Multiprocessor
IEEE Design & Test
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Practical asynchronous interconnect network design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multisynchronous and Fully Asynchronous NoCs for GALS Architectures
IEEE Design & Test
Integration, the VLSI Journal
Characterization of Asynchronous Templates for Integration into Clocked CAD Flows
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A fully-asynchronous low-power framework for GALS NoC integration
Proceedings of the Conference on Design, Automation and Test in Europe
A low-latency adaptive asynchronous interconnection network using bi-modal router nodes
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
High-Performance Asynchronous Pipelines: An Overview
IEEE Design & Test
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits
ASYNC '12 Proceedings of the 2012 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
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Asynchronous networks-on-chip (NoCs) are an appealing solution to tackle the synchronization challenge in modern multicore systems through the implementation of a GALS paradigm. However, they have found only limited applicability so far due to two main reasons: the lack of proper design tool flows as well as their significant area footprint over their synchronous counterparts. This paper proposes a largely unexplored design point for asynchronous NoCs, relying on transition-signaling bundled data, which contributes to break the above barriers. Compared to an existing lightweight synchronous switch architecture, xpipesLite, the post-layout asynchronous switch achieved a 71% reduction in area, up to 85% reduction in overall power consumption, and a 44% average reduction in energy-per-flit, while mastering the more stringent timing assumptions of this solution with a semi-automated synthesis flow.