Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
A globally asynchronous locally dynamic system for ASICs and SoCs
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Highly Scalable GALS Crossbar Using Token Ring Arbitration
IEEE Design & Test
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents several new asynchronous FIFO designs. While most existing FIFO's trade higher throughput for higher latency, our goal is to achieve very low latency while maintaining good throughput. The designs are implemented as circular arrays of cells connected to common data buses. Data items are not moved around the array once they are enqueued. Each cell's input and output behavior is dictated by the flow of two tokens around the ring: one that allows enqueuing data and one that allows dequeuing data. Two novel protocols are introduced with various degrees of parallelism, as well as four different implementations. The best simulation results, in 0.6 micron, have a latency of 1.73ns and throughput of 454 MegaOperations/second for a 4-place FIFO.