Communications of the ACM
Low power design in deep submicron electronics
Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Interfacing synchronous and asynchronous modules within a high-speed pipeline
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Micronetwork-based integration for SOCs: 673
Proceedings of the 38th annual Design Automation Conference
Power and performance evaluation of globally asynchronous locally synchronous processors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools
Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Pausible Clocking: A First Step Toward Heterogeneous Systems
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Synthesis of Asynchronous State Machines Using A Local Clock
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Low-Latency Asynchronous FIFO's Using Token Rings
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Point to Point GALS Interconnect
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Timing Measurements of Synchronization Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Congestion and Starvation Detection in Ripple FIFOs
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A Low-Latency FIFO for Mixed-Clock Systems
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Asynchronous Wrapper for Heterogeneous Systems
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Automatic Synthesis of Burst-Mode Asynchronous Controllers
Automatic Synthesis of Burst-Mode Asynchronous Controllers
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal path routing in single- and multiple-clock domain systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GALS networks on chip: a new solution for asynchronous delay-insensitive links
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
Tartan: evaluating spatial computation for whole program execution
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Adaptive Latency-Insensitive Protocols
IEEE Design & Test
Dataflow Architectures for GALS
Electronic Notes in Theoretical Computer Science (ENTCS)
Practical asynchronous interconnect network design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transactions on Petri Nets and Other Models of Concurrency I
A trace-based framework for verifiable GALS composition of IPs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
A modular synchronizing FIFO for NoCs
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the 2nd International Workshop on Network on Chip Architectures
The Role of Back-Pressure in Implementing Latency-Insensitive Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Programmable logic core enhancements for high-speed on-chip interfaces
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 7th ACM international conference on Computing frontiers
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A fully-asynchronous low-power framework for GALS NoC integration
Proceedings of the Conference on Design, Automation and Test in Europe
A general method to make multi-clock system deterministic
Proceedings of the Conference on Design, Automation and Test in Europe
System-level process variability analysis and mitigation for 3D MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
A hardwired NoC infrastructure for embedded systems on FPGAs
Microprocessors & Microsystems
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous switching for low-power networks-on-chip
Microelectronics Journal
A novel hybrid FIFO asynchronous clock domain crossing interfacing method
Proceedings of the great lakes symposium on VLSI
Proceedings of the Conference on Design, Automation and Test in Europe
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
StarSync: An extendable standard-cell mesochronous synchronizer
Integration, the VLSI Journal
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This paper presents several low-latency mixed-timing FIFO (first-in-first-out) interfaces designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The designs are then adapted to work between systems with very long interconnect delays, by migrating a single-clock solution by Carloni et al. (1999, 2000, and 2001) (for "latency-insensitive" protocols) to mixed-timing domains. The new designs can be made arbitrarily robust with regard to metastability and interface operating speeds. Initial simulations for both latency and throughput are promising.