Digital systems engineering
Stretching quasi delay insensitivity by means of extended isochronic forks
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A predictive synchronizer for periodic clock domains
Formal Methods in System Design
Computing synchronizer failure probabilities
Proceedings of the conference on Design, automation and test in Europe
Integration, the VLSI Journal
Measuring deep metastability and its effect on synchronizer performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the 2nd International Workshop on Network on Chip Architectures
From synchronous to GALS: A new architecture for FPGAs
Microelectronics Journal
A Metastability-Free Multi-synchronous Communication Scheme for SoCs
SSS '09 Proceedings of the 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault-tolerant algorithms for tick-generation in asynchronous logic: robust pulse generation
SSS'11 Proceedings of the 13th international conference on Stabilization, safety, and security of distributed systems
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
HEX: scaling honeycombs is easier than scaling clock trees
Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures
StarSync: An extendable standard-cell mesochronous synchronizer
Integration, the VLSI Journal
Journal of Computer and System Sciences
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A regular (two-flop) synchronizer and six multi-synchronous synchronizers are implemented on a programmable logic device and are measured. An experiment system and method for measuring synchronizers and metastable flip-flops are described. Two separate settling time constants are shown for a metastable flop, confirming earlier results of Dike and Burton [1]. Clocking cross-talk between asynchronous clocks is demonstrated. The regular synchronizer is useful for communications between asynchronous clock domains, while the other synchronizers can provide higher bandwidth communications between multi-synchronous and mesochronous domains.