Introduction to VLSI Systems
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Timing Measurements of Synchronization Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Analysis and Design of Digital Integrated Circuits
Analysis and Design of Digital Integrated Circuits
Proceedings of the 44th annual Design Automation Conference
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
A modular synchronizing FIFO for NoCs
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Synchronization and Arbitration in GALS
Electronic Notes in Theoretical Computer Science (ENTCS)
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
Microelectronics Journal
Metastability challenges for 65nm and beyond: simulation and measurements
Proceedings of the Conference on Design, Automation and Test in Europe
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System-on-Chip designs often have a large number of timing domains. Communication between these domains requires synchronization, and the failure probabilities of these synchronizers must be characterized accurately to ensure the robustness of the complete system. We present a novel approach for determining the failure probabilities of synchronizer circuits. Our approach using numerical integration to account for the nonlinear behaviour of real synchronizer circuits. We complement this with small-signal techniques to enable accurate estimation of extremely small failure probabilities. Our approach is fully automated, is suitable for integration into circuit simulation tools such as SPICE and enables accurate characterization of extremely small failure probabilities.