The design of a high performance low power microprocessor
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Introduction to VLSI Systems
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Noise margin analysis for dynamic logic circuits
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Computing synchronizer failure probabilities
Proceedings of the conference on Design, automation and test in Europe
Anomalous Behavior of Synchronizer and Arbiter Circuits
IEEE Transactions on Computers
Analysis and Design of Digital Integrated Circuits
Analysis and Design of Digital Integrated Circuits
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
Truncation error analysis of MTBF computation for multi-latch synchronizers
Microelectronics Journal
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Circuits such as flip-flops, sense amplifiers and synchronizers can exhibit metastability failures that are undetectable given the numerical accuracy limitations of simulators such as HSPICE. We present a novel simulation technique that allows us to generate accurate waveforms for the metastability failures and similar events. We apply our method to two latches and a self-resetting circuit for clock-phase generation.