Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Output Prediction Logic: A High-Performance CMOS Design Technique
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Proceedings of the 44th annual Design Automation Conference
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We consider the problem of noise margin analysis for dynamic logic circuits. Because such circuits operate in multiple phases, their noise immunity is also time varying. We formulate noise margin analysis as a non-linear optimization problem where we find the smallest disturbance waveform that results in a qualitative change in the behavior of the circuit. We present a practical method for solving these optimization problems based on deriving a sensitivity matrix for the small-signal response of the circuit. We use our approach to compare the robustness of static CMOS gates, self-resetting domino, and output prediction logic.