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Characterization of logic circuit techniques for high leakage CMOS technologies
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
High Speed Redundant Adder and Divider in Output Prediction Logic
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Noise margin analysis for dynamic logic circuits
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present Output Prediction Logic (OPL), a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the restoring character of the logic family, including its high noise margins. Speedups of 2 X to 3 X over (optimized) conventional static CMOS are demonstrated for a variety of circuits, ranging from chains of gates, to datapath circuits, and to random logic benchmarks. Such speedups are obtained using identical netlists without remapping. When applied to pseudo-nMOS and dynamic families, in combination with remapping to wide-input NORs, OPL yields speedups of 4 X to 5 X over static CMOS. Since OPL applied to static CMOS is faster than conventional domino logic, and since it has higher noise margins than domino logic, we believe it will scale much better than domino with future processing technologies.