Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Digital systems engineering
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Skew-tolerant circuit design
Statistical clock skew modeling with data delay variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Introduction to VLSI Systems
IC power distribution challenges
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Clock-Delayed Domino for Adder and Combinational Logic Desig
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Design and Synthesis of Monotonic Circuits
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Output Prediction Logic: A High-Performance CMOS Design Technique
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Timing analysis including clock skew
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Structured and tuned array generation (STAG) for high-performance random logic
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Low power dynamic logic circuit design using a pseudo dynamic buffer
Integration, the VLSI Journal
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In order for dynamic circuits to operate correctly, their inputs must be monotonically rising during evaluation. Blocking dynamic circuits satisfy this constraint by delaying evaluation until all inputs have been properly setup relative to the evaluation clock. By viewing dynamic gates as latches, we demonstrate that the optimal delay of a blocking dynamic gate may occur when the setup time is negative. With blocking dynamic circuits, cascading low-skew dynamic gates allows each dynamic gate to tolerate a degraded input level. The larger noise margin provides greater flexibility with the delay versus noise margin tradeoff (i.e., the circuit robustness versus speed tradeoff). This paper generalizes blocking dynamic circuits and provides a systematic approach for assigning clock phases, given delay and noise margin constraints. Using this framework, one can analyze any logic network consisting of blocking dynamic circuits.