Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logic
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Analysis of blocking dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Synthesis of skewed logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integer linear programming-based synthesis of skewed logic circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Characteristics of MS-CMOS logic in sub-32nm technologies
Proceedings of the 20th symposium on Great lakes symposium on VLSI
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We developed a methodology and tools for synthesizing monotonic networks, which consist of alternating low-skew and high-skew logic gates. By taking advantage of their reduced input capacitance, lower switching thresholds, and efficient implementation for wide complex gates, monotonic circuits can obtain greater performance compared to static CMOS. Our results show standard domino, dynamic-static domio, monotonic static CMOS, and zipper CMOS to have average speed improvements of 1.57, 1.66, 1.67, and 1.47 times over static CMOS, respectively.