Monotonic static CMOS and dual-VT technology
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Design and Synthesis of Monotonic Circuits
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Characterization of monotonic static CMOS gates in a 65nm technology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Monotonic static CMOS tradeoffs in sub-100nm technologies
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Enhanced leakage reduction techniques using intermediate strength power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
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This paper explores the characteristics of Monotonic-Static CMOS and its potential applications in gate leakage reduction in a hypothetical 22nm Bulk-Si technology with significant gate leakage currents. Using test circuits consisting of NAND and NOR logic gates, we performed a comparison among static, monotonic static and domino logic in terms of various properties including power, delay, noise margin and area. Comparisons were done over a wide range of possible transistor widths to fully characterize the tradeoffs for each circuit type. Experimental results show that MS-CMOS has potential advantages in terms of stand-by power, evaluation speed and noise margin in such a technology.