MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Enchanced multi-threshold (MTCMOS) circuits using variable well bias
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Proceedings of the 39th annual Design Automation Conference
Design Challenges of Technology Scaling
IEEE Micro
Analysis of Ground Bounce in Deep Sub-Micron Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
Design and CAD Challenges in sub-90nm CMOS Technologies
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Experimental measurement of a novel power gating structure with intermediate power saving mode
Proceedings of the 2004 international symposium on Low power electronics and design
An effective power mode transition technique in MTCMOS circuits
Proceedings of the 42nd annual Design Automation Conference
Dynamic virtual ground voltage estimation for power gating
Proceedings of the 13th international symposium on Low power electronics and design
Design of a flexible reactivation cell for safe power-mode transition in power-gated circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Temporal and spatial idleness exploitation for optimal-grained leakage control
Proceedings of the 2009 International Conference on Computer-Aided Design
Characteristics of MS-CMOS logic in sub-32nm technologies
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A three-step power-gating turn-on technique for controlling ground bounce noise
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic characteristics of power gating during mode transition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the International Conference on Computer-Aided Design
A semiempirical model for wakeup time estimation in power-gated logic clusters
Proceedings of the 49th Annual Design Automation Conference
Adaptive power management of on-chip video memory for multiview video coding
Proceedings of the 49th Annual Design Automation Conference
TAP: token-based adaptive power gating
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Self-adaptive hybrid dynamic power management for many-core systems
Proceedings of the Conference on Design, Automation and Test in Europe
Using synchronization stalls in power-aware accelerators
Proceedings of the Conference on Design, Automation and Test in Europe
Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding
Proceedings of the Conference on Design, Automation and Test in Europe
Testing for SoCs with advanced static and dynamic power-management capabilities
Proceedings of the Conference on Design, Automation and Test in Europe
Threshold voltage tuning for faster activation with lower noise in tri-mode MTCMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-efficient error-resiliency for H.264/AVC context-adaptive variable length coding
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
MAPG: memory access power gating
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
AMBER: adaptive energy management for on-chip hybrid video memories
Proceedings of the International Conference on Computer-Aided Design
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The exponential increase in leakage power due to technology scaling has made power gating an attractive design choice for low-power applications. In this paper, we explore this design style in large combinational circuit blocks and latch-to-latch datapaths and introduce a novel power gating approach to yield an improved power-performance tradeoff. We first present a multiple sleep mode power gating technique where each mode represents a different point in the wake-up overhead versus leakage savings design space. We show that the high wake-up latency and wakeup power penalty of traditional power gating limits its application to large stretches of inactivity. The multiple-mode feature allows a processor to enter power saving modes more frequently, hence, resulting in enhanced leakage savings. We apply the multimode power gating technique to datapaths where the degree of applied power gating becomes progressively stronger (harder) along the datapath. This configuration allows us to further balance wakeup overhead with leakage savings by exploiting the fact that logic circuits deep in the datapath have higher wakeup margin and hence can be strongly gated. Simulations show that multiple sleep mode capability provides an extra 17% reduction in overall leakage compared to traditional single mode gating. The multiple modes can be designed to allow state-retentive modes. The results on benchmarks show that a single state-retentive mode can reduce leakage by 19% while preserving state of the circuit.