Threshold voltage tuning for faster activation with lower noise in tri-mode MTCMOS circuits

Authors:
Hailong Jiao;Volkan Kursun
Affiliations:
Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Kowloon, Hong Kong;Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Kowloon, Hong Kong
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

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Abstract

A new threshold voltage tuning methodology is explored in this paper to minimize the peak power/ground bouncing noise with smaller sleep transistors in multi-threshold CMOS (MTCMOS) circuits. Different circuit techniques with the threshold voltage tuning strategy lower the activation noise, the activation delay, and the size of the additional sleep transistors by up to 27.76%, 32.66%, and 85.71%, respectively, as compared to a previously published noise-aware MTCMOS circuit with standard zero-body-biased high threshold voltage sleep transistors in a UMC 80-nm CMOS technology.