Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Leakage control with efficient use of transistor stacks in single threshold CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic fine-grain leakage reduction using leakage-biased bitlines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Standby power management for a 0.18μm microprocessor
Proceedings of the 2002 international symposium on Low power electronics and design
Circuit-level techniques to control gate leakage for sub-100nm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Design Challenges of Technology Scaling
IEEE Micro
Optimizing Static Power Dissipation by Functional Units in Superscalar Processors
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Managing static leakage energy in microprocessor functional units
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Representative Traces for Processor Models with Infinite Cache
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
POWER4 system microarchitecture
IBM Journal of Research and Development
Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Compilation for compact power-gating controls
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Run-time power gating of on-chip routers using look-ahead routing
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Accurate energy breakeven time estimation for run-time power gating
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cache Controller Design on Ultra Low Leakage Embedded Processors
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Dynamic power gating with quality guarantees
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
A DVS-based pipelined reconfigurable instruction memory
Proceedings of the 46th Annual Design Automation Conference
Segment gating for static energy reduction in Networks-on-Chip
Proceedings of the 2nd International Workshop on Network on Chip Architectures
RTL power modeling and estimation of sleep transistor based power gating
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Reducing peak power with a table-driven adaptive processor core
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A cost-effective load-balancing policy for tile-based, massive multi-core packet processors
ACM Transactions on Embedded Computing Systems (TECS)
Low-power TinyOS tuned processor platform for wireless sensor network motes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Automated power gating of registers using CoDeL and FSM branch prediction
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Power-efficient, reliable microprocessor architectures: modeling and design methods
Proceedings of the 20th symposium on Great lakes symposium on VLSI
The challenges of implementing fine-grained power gating
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Compiler-directed leakage reduction in embedded microprocessors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
WiDGET: Wisconsin decoupled grid execution tiles
Proceedings of the 37th annual international symposium on Computer architecture
Hardware-based load balancing for massive multicore architectures implementing power gating
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing functional unit power consumption and its variation using leakage sensors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A power-efficient network on-chip topology
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
On the power management of simultaneous multithreading processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design constraint of fine grain supply voltage control LSI
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A framework for power-gating functional units in embedded microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of an ultra low leakage buffer chain
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
Dynamic characteristics of power gating during mode transition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Curbing energy cravings in networks: a cross-sectional view across the micro-macro boundary
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
On-chip detection methodology for break-even time of power gated function units
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Power gating strategies on GPUs
ACM Transactions on Architecture and Code Optimization (TACO)
ACM Transactions on Architecture and Code Optimization (TACO)
A case for NEMS-based functional-unit power gating of low-power embedded microprocessors
Proceedings of the 48th Design Automation Conference
FlexiBuffer: reducing leakage power in on-chip network routers
Proceedings of the 48th Design Automation Conference
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power management and its impact on power supply noise
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
SIMD defragmenter: efficient ILP realization on data-parallel architectures
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Reducing execution unit leakage power in embedded processors
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Guarded power gating in a multi-core setting
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
Stepwise sleep depth control for run-time leakage power saving
Proceedings of the great lakes symposium on VLSI
A semiempirical model for wakeup time estimation in power-gated logic clusters
Proceedings of the 49th Annual Design Automation Conference
TAP: token-based adaptive power gating
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Adopting TLB index-based tagging to data caches for tag energy reduction
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
RTL power modeling and estimation of sleep transistor based power gating
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Power devil: tool for power gating strategy selection
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Catnap: energy proportional multiple network-on-chip
Proceedings of the 40th Annual International Symposium on Computer Architecture
Threshold voltage tuning for faster activation with lower noise in tri-mode MTCMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Formal verification of architectural power intent
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power management of multi-core chips: challenges and pitfalls
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
MAPG: memory access power gating
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
ELEON3LP - Superscalar and low-power enhancements of single issue general purpose processor model
Microprocessors & Microsystems
Warped gates: gating aware scheduling and power gating for GPGPUs
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Power-aware code scheduling assisted with power gating and DVS
Future Generation Computer Systems
Energy and throughput aware fuzzy logic based reconfiguration for MPSoCs
Journal of Intelligent & Fuzzy Systems: Applications in Engineering and Technology
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Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of execution units. This paper first develops parameterized analytical equations that estimate the break-even point for application of power-gating techniques. The potential for power gating execution units is then evaluated, for the range of relevant break-even points determined by the analytical equations, using a state-of-the-art out-of-order superscalar processor model. The power gating potential of the floating-point and fixed-point units of this processor is then evaluated using three different techniques to detect opportunities for entering sleep mode; ideal, time-based, and branch-misprediction-guided. Our results show that using the time-based approach, floating-point units can be put to sleep for up to 28% of the execution cycles at a performance loss of 2%. For the more difficult to power-gate fixed-point units, the branch misprediction guided technique allows the fixed-point units to be put to sleep for up to 40% more of the execution cycles compared to the simpler time-based technique, with similar performance impact. Overall, our experiments demonstrate that architectural techniques can be used effectively in power-gating execution units.