Power devil: tool for power gating strategy selection

  • Authors:
  • Jen Huang;Huang-Jia Cheng;Yuan-Shin Hwang

  • Affiliations:
  • National Taiwan University of Science and Technology, Taipei, Taiwan;National Taiwan University of Science and Technology, Taipei, Taiwan;National Taiwan University of Science and Technology, Taipei, Taiwan

  • Venue:
  • Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
  • Year:
  • 2013

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Abstract

Reducing leakage power of embedded systems is essential as it constitutes an increasing fraction of the total power consumption in modern embedded processors. Power gating of functional units has been proved to be an effective technique to reduce leakage, and its various implementations can be categorized into compiler-based and hardware-based approaches. Hardware-only designs rely on specific circuits and microarchitectural designs to monitor instruction executions to determine when to power-gate functional units, whereas compiler-based methods attempt to exploit global information of programs and let compilers embed special instructions to turn on and off functional units. Previous studies have shown that the hardware-only approach is generally effective in reducing leakage, while the compiler-based approach occasionally performs better as the global knowledge of programs gathered by compilers would avoid incurring excessive power gating on/off activities. This outcome suggests a better scheme: a hardware-based technique is deployed as the default power gating mechanism, and a compiler would intervene only when its analysis indicates the default method is inferior for certain application programs. The missing link of this scheme is a tool to identify such a situation, and this paper presents a tool called Power Devil as the remedy.