Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Life is CMOS: why chase the life after?
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 40th annual Design Automation Conference
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Enabling on-chip diversity through architectural communication design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Circuit and Platform Design Challenges in Technologies beyond 90nm
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Scaling into Ambient Intelligence
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 42nd annual Design Automation Conference
Understanding the energy efficiency of SMT and CMP with multiclustering
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Advanced power management techniques: going beyond intelligent shutdown
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
VLSI on-chip power/ground network optimization considering decap leakage currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Towards formal probabilistic power-performance design space exploration
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
LVS verification across multiple power domains for a quad-core microprocessor
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Compilation for compact power-gating controls
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Leakage current optimization techniques during test based on don't care bits assignment
Journal of Computer Science and Technology
Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion
Proceedings of the 13th international symposium on Low power electronics and design
Profit aware circuit design under process variations considering speed binning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An MTCMOS technology for low-power physical design
Integration, the VLSI Journal
The epsilon-approximation to discrete VT assignment for leakage power minimization
Proceedings of the 2009 International Conference on Computer-Aided Design
The synthesis of combinational logic to generate probabilities
Proceedings of the 2009 International Conference on Computer-Aided Design
The next generation challenge for software defined radio
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Performance and power evaluation of an intelligently adaptive data cache
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
Computation of joint timing yield of sequential networks considering process variations
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Exploiting input variations for energy reduction
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Power devil: tool for power gating strategy selection
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
Profit maximization through process variation aware high level synthesis with speed binning
Proceedings of the Conference on Design, Automation and Test in Europe
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Future high performance microprocessor design with technology scaling beyond 90nm will pose two major challenges: (1) energy and power, and (2) parameter variations. Design practice will have to change from deterministic design to probabilistic and statistical design. This paper discusses circuit techniques and design automation opportunities to overcome the challenges.