Sub-90nm technologies: challenges and opportunities for CAD
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A low-power VLSI architecture for turbo decoding
Proceedings of the 2003 international symposium on Low power electronics and design
Energy efficiency vs. programmability trade-off: architectures and design principles
Proceedings of the conference on Design, automation and test in Europe: Proceedings
SODA: A Low-power Architecture For Software Radio
Proceedings of the 33rd annual international symposium on Computer Architecture
A Low-Power Multithreaded Processor for Software Defined Radio
Journal of VLSI Signal Processing Systems
Reliability challenges for 45nm and beyond
Proceedings of the 43rd annual Design Automation Conference
A VLSI Architecture of the Square Root Algorithm for V-BLAST Detection
Journal of VLSI Signal Processing Systems
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)
Proceedings of the 2006 international symposium on Low power electronics and design
Software defined radio – a high performance embedded challenge
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
A simple transmit diversity technique for wireless communications
IEEE Journal on Selected Areas in Communications
Wireless innovation through software radios
ACM SIGCOMM Computer Communication Review
AnySP: anytime anywhere anyway signal processing
Proceedings of the 36th annual international symposium on Computer architecture
Implementation of a 2 × 2 MIMO-OFDM receiver on an application specific processor
Microelectronics Journal
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Analyzing the Next Generation Software Defined Radio for Future Architectures
Journal of Signal Processing Systems
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Wireless communication for mobile terminals has been a high performance computing challenge. It requires almost super computer performance while consuming very little power. This requirement is being made even more challenging with the move to Fourth Generation (4G) wireless communication. It is projected that by 2010, 4G will be available with data rates from 100Mbps to 1Gbps. These data rates are orders of magnitude greater than current 3G technology and, consequently, will require orders of magnitude more computation power. Leading forerunners for this technology are protocols like 802.16e (mobile WiMAX) and 3GPP LTE. This paper presents an analysis of the major algorithms that comprise these 4G technologies and describes their computational characteristics. We identify the major bottlenecks that need to be overcome in order to meet the requirements of this new technology. In particular, we show that technology scaling alone of current Software Defined Radio architectures will not be able to meet these requirements. Finally, we will discuss techniques that may make it possible to meet the power/performance requirements without giving up programmability.