on Parallel MIMD computation: HEP supercomputer and its applications
Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
ICS '90 Proceedings of the 4th international conference on Supercomputing
Parallel saturating multioperand adders
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
DSP Processor Fundamentals: Architectures and Features
DSP Processor Fundamentals: Architectures and Features
The TigerSHARC DSP Architecture
IEEE Micro
NetBeans: The Definitive Guide
NetBeans: The Definitive Guide
A survey of processors with explicit multithreading
ACM Computing Surveys (CSUR)
Embedded processor design challenges
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
A New Approach to DSP Intrinsic Functions
HICSS '00 Proceedings of the 33rd Hawaii International Conference on System Sciences-Volume 8 - Volume 8
A Multithreaded Java Microcontroller for Thread-Oriented Real-Time Event Handling
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
MPEG-2 Video Decompression on Simultaneous Multithreaded Multimedia Processors
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Power-Sensitive Multithreaded Architecture
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
EVALUATING AND IMPROVING PERFORMANCE OF MULTIMEDIA APPLICATIONS ON SIMULTANEOUS MULTI-THREADING
ICPADS '02 Proceedings of the 9th International Conference on Parallel and Distributed Systems
Design Alternatives for Parallel Saturating Multioperand Adders
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
A Low-Power Multithreaded Processor for Software Defined Radio
Journal of VLSI Signal Processing Systems
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Reconfigurable terminals: an overview of architectural solutions
IEEE Communications Magazine
A software-defined communications baseband design
IEEE Communications Magazine
A Low-Power Multithreaded Processor for Software Defined Radio
Journal of VLSI Signal Processing Systems
An integrated ARM and multi-core DSP simulator
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
A New Era of Performance Evaluation
Computer
Amdahl's law revisited for single chip systems
International Journal of Parallel Programming
The next generation challenge for software defined radio
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
International Journal of High Performance Systems Architecture
CORDIC instruction set extensions for matrix decompositions on software defined radio processors
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Domain specific architecture for next generation wireless communication
Proceedings of the Conference on Design, Automation and Test in Europe
Design of an application-specific instruction set processor for high-throughput and scalable FFT
Proceedings of the Conference on Design, Automation and Test in Europe
A multithreaded multicore system for embedded media processing
Transactions on high-performance embedded architectures and compilers III
CORDIC instructions for LDPC decoding on SDR platforms
Analog Integrated Circuits and Signal Processing
Instruction Set Extensions for Matrix Decompositions on Software Defined Radio Architectures
Journal of Signal Processing Systems
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Embedded digital signal processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for software defined radio. The processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the processor's architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the processor's programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the processor also provides efficient support for a wide variety of digital signal processing and multimedia applications.