Low delay spread multi-path cancellation for 3G WCDMA
WISICT '04 Proceedings of the winter international synposium on Information and communication technologies
A low-power memory hierarchy for a fully programmable baseband processor
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
Future wireless convergence platforms
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Instruction set extensions for software defined radio on a multithreaded processor
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
A Low-Power Multithreaded Processor for Software Defined Radio
Journal of VLSI Signal Processing Systems
Reducing idle mode power in software defined radio terminals
Proceedings of the 2006 international symposium on Low power electronics and design
Vector processing as an enabler for software-defined radio in handheld devices
EURASIP Journal on Applied Signal Processing
An integrated ARM and multi-core DSP simulator
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Beyond third generation (B3G) mobile communication: challenges, broadband access and Europe
Mobility '06 Proceedings of the 3rd international conference on Mobile technology, applications & systems
Reconfigurable wireless handset realization based on a universal API
ICCOM'07 Proceedings of the 11th Conference on 11th WSEAS International Conference on Communications - Volume 11
EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
A coarse-grained array based baseband processor for 100Mbps+ software defined radio
Proceedings of the conference on Design, automation and test in Europe
Instruction set extensions for software defined radio
Microprocessors & Microsystems
ICCOM'08 Proceedings of the 12th WSEAS international conference on Communications
Trends in low power handset software defined radio
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Area efficient fully programmable baseband processors
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Multimode flex-interleaver core for baseband processor platform
Journal of Computer Systems, Networks, and Communications - Special issue on WiMAX, LTE, and WiFi interworking
A low-power DSP for wireless communications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy Aware Signal Processing for Software Defined Radio Baseband Implementation
Journal of Signal Processing Systems
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Software implementation of WiMAX on the sandbridge sandblaster platform
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A 100 GOPS ASP based baseband processor for wireless communication
Proceedings of the Conference on Design, Automation and Test in Europe
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Software-defined radios offer a programmable and dynamically reconfigurable method of reusing hardware to implement the physical layer processing of multiple communications systems. An SDR can dynamically change protocols and update communications systems over the air as a service provider allows. In this article we discuss a baseband solution for an SDR system and describe a 2 Mb/s WCDMA design with GSM/GPRS and 802.11b capability that executes all physical layer processing completely in software. We describe the WCDMA communications protocols with a focus on latency reduction and unique implementation techniques. We also describe the underlying technology that enables software execution. Our solution is programmed in C and executed on a multithreaded processor in real time.