Java intermediate bytecodes: ACM SIGPLAN workshop on intermediate representations (IR'95)
IR '95 Papers from the 1995 ACM SIGPLAN workshop on Intermediate representations
LISA—machine description language for cycle-accurate models of programmable DSP architectures
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Computer Architecture: Concepts and Evolution
Computer Architecture: Concepts and Evolution
An ultra-fast instruction set simulator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Delft-Java Engine: An Introduction
Euro-Par '97 Proceedings of the Third International Euro-Par Conference on Parallel Processing
A Framework for Simulating Heterogeneous Virtual Processors
SS '99 Proceedings of the Thirty-Second Annual Simulation Symposium
Shade: A Fast Instruction Set Simulator for Execution Profiling
Shade: A Fast Instruction Set Simulator for Execution Profiling
Automated generation of DSP program development tools using a machine description formalism
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
A software-defined communications baseband design
IEEE Communications Magazine
A Low-Power Multithreaded Processor for Software Defined Radio
Journal of VLSI Signal Processing Systems
Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures
Journal of Systems Architecture: the EUROMICRO Journal
An integrated ARM and multi-core DSP simulator
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Reconfigurable wireless handset realization based on a universal API
ICCOM'07 Proceedings of the 11th Conference on 11th WSEAS International Conference on Communications - Volume 11
EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
International Journal of High Performance Systems Architecture
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Analog Integrated Circuits and Signal Processing
Instruction Set Extensions for Matrix Decompositions on Software Defined Radio Architectures
Journal of Signal Processing Systems
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We describe the generation of the simulation environment for the Sandbridge Sandblaster multithreaded processor. The processor model is described using the Sandblaster architecture Description Language (SaDL), which is implemented as python objects. Specific processor implementations of the simulation environment are generated by calling the python objects. Using just-in-time compiler technology, we dynamically compile an executing program and processor model to a target platform, providing fast interactive responses with accelerated simulation capability. Using this approach, we simulate up to 100 million instructions per second on a 1 GHz Pentium processor. This allows the system programmer to prototype many applications in real-time within the simulation environment, providing a dramatic increase in productivity and allowing flexible hardware-software trade-offs.