Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
Securing wireless data: system architecture challenges
Proceedings of the 15th international symposium on System Synthesis
A Compact Rijndael Hardware Architecture with S-Box Optimization
ASIACRYPT '01 Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
Efficient AES implementations for ARM based platforms
Proceedings of the 2004 ACM symposium on Applied computing
Fast Parallel Table Lookups to Accelerate Symmetric-Key Cryptography
ITCC '05 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume I - Volume 01
Instruction set extensions for software defined radio on a multithreaded processor
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Towards a fraud-prevention framework for software defined radio mobile devices
EURASIP Journal on Wireless Communications and Networking
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
A Low-Power Multithreaded Processor for Software Defined Radio
Journal of VLSI Signal Processing Systems
An integrated ARM and multi-core DSP simulator
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Accelerating AES using instruction set extensions for elliptic curve cryptography
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part II
Instruction set extensions for efficient AES implementation on 32-bit processors
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
SP 800-97. Establishing Wireless Robust Security Networks: A Guide to IEEE 802.11i
SP 800-97. Establishing Wireless Robust Security Networks: A Guide to IEEE 802.11i
Reconfigurable terminals: an overview of architectural solutions
IEEE Communications Magazine
An improved wideband CIC filter design of software radio receivers
International Journal of Wireless and Mobile Computing
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Software-defined radio (SDR) is an emerging technology that facilitates having multiple wireless communication protocols on one device. Previous work has shown that current wireless communication protocols can run on this class of device while consuming significant processing power. Next generation wireless networks require speeds in excess of 50 Mbps. Some of the fastest software implementations of the advanced encryption standard (AES) only achieve 20 Mbps on our reference platform. In order to have secure software-defined radio, the security processing gap must be addressed. This paper presents instruction set architecture (ISA) extensions for the sandblaster digital signal processor (DSP). The sandblaster DSP is a multithreaded processor for SDR that issues multiple operations each cycle and supports vector operations. Our proposed ISA extensions and hardware designs provide significant performance improvements for AES cryptography and should also work well with other types of embedded processors.