Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction Set Extensions for Reed-Solomon Encoding and Decoding
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Reconfigurable terminals: an overview of architectural solutions
IEEE Communications Magazine
A software-defined communications baseband design
IEEE Communications Magazine
Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New architectures for fast convolutional encoders and threshold decoders
IEEE Journal on Selected Areas in Communications
Instruction set extensions for software defined radio
Microprocessors & Microsystems
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
High-bandwidth address generation unit
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
International Journal of High Performance Systems Architecture
Instructions and hardware designs for accelerating SNOW 3G on a software-defined radio platform
Analog Integrated Circuits and Signal Processing
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Software defined radios, which provide a programmable solution for implementing the physical layer processing of multiple communication standards, are widely recognized as one of the most important new technologies for wireless communication systems. Emerging communication standards, however, require tremendous processing capabilities to perform high-bandwidth physical-layer processing in real time. In this paper, we present instruction set extensions for several important communication algorithms including convolutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. The performance benefits of these extensions are evaluated using a supercomputer class vectorizing compiler and the Sandblaster low-power multithreaded processor for software defined radio. The proposed instruction set extensions provide significant performance improvements, while maintaining a high degree of programmability.