Instruction set extensions for software defined radio on a multithreaded processor
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
CReconfigurable finite field instruction set architecture
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Experiences with a FPGA-based Reed/Solomon-encoding coprocessor
Microprocessors & Microsystems
Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Instruction set extensions for software defined radio
Microprocessors & Microsystems
FPGA-accelerated deletion-tolerant coding for reliable distributed storage
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
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Reed-Solomon codes are an important class of error correcting codes used in many applications related to communications and digital storage. The fundamental operations in Reed-Solomon encoding and decoding involve Galois field arithmetic which is not directly supported in general purpose processors. On the other hand, pure hardware implementations of Reed-Solomon coders are not programmable. In this paper, we present a novel algorithm to performReed-Solomon encoding. We also propose four new instructions for Galois field arithmetic. We show that by using the instructions, we can speedup Reed-Solomon decoding by a factor of 12 compared to a pure software approach, while still maintaining programmability.