Coding and information theory
A tutorial on Reed-Solomon coding for fault-tolerance in RAID-like systems
Software—Practice & Experience
IEEE Transactions on Computers
Reconfigurable Implementation of Elliptic Curve Crypto Algorithms
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Fault-Tolerant Distributed Mass Storage for LHC Computing
CCGRID '03 Proceedings of the 3st International Symposium on Cluster Computing and the Grid
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Instruction Set Extensions for Reed-Solomon Encoding and Decoding
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
High Performance Linear Algebra Operations on Reconfigurable Systems
SC '05 Proceedings of the 2005 ACM/IEEE conference on Supercomputing
FPGA based RAID 6 hardware accelerator
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Comparison of Redundancy Schemes for Distributed Storage Systems
NCA '06 Proceedings of the Fifth IEEE International Symposium on Network Computing and Applications
Data consistent up- and downstreaming in a distributed storage system
SNAPI '03 Proceedings of the international workshop on Storage network architecture and parallel I/Os
Architectures and APIs: assessing requirements for delivering FPGA performance to applications
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
PVFS: a parallel file system for linux clusters
ALS'00 Proceedings of the 4th annual Linux Showcase & Conference - Volume 4
FPGA-accelerated deletion-tolerant coding for reliable distributed storage
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
An iterative logarithmic multiplier
Microprocessors & Microsystems
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In this paper we present an implementation of a Reed/Solomon (R/S)-coprocessor to be used on a hybrid computing system, which combines general purpose CPUs with FPGAs. The coprocessor accelerates the encoding of user data to be stored block-wise on a distributed, failure-tolerant storage system. We document design constraints and their impact on the resulting architecture. Measurements are presented to characterize the performance of the coprocessor in terms of computational bandwidth, latency, and the hardware-software interaction. For comparison, software-based R/S-encoding implementations are presented and evaluated as well. The two variants of the FPGA-based coprocessors are compared to each other with respect to their fitting to a distributed storage application.