Error control systems for digital communication and storage
Error control systems for digital communication and storage
Implementing elliptic curve cryptography
Implementing elliptic curve cryptography
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Subword Parallelism with MAX-2
IEEE Micro
VLSI Algorithms, Architectures, and Implementation of a Versatile GF(2m) Processor
IEEE Transactions on Computers
On Computing Multiplicative Inverses in GF(2/sup m/)
IEEE Transactions on Computers
Experiences with a FPGA-based Reed/Solomon-encoding coprocessor
Microprocessors & Microsystems
FPGA-accelerated deletion-tolerant coding for reliable distributed storage
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
Applying error correction codes to achieve security and dependability
Computer Standards & Interfaces
| Hi-index | 0.00 |
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m), such as RS and BCH codes, Elliptic Curve Cryptography and the AES. Complexities of flexible implementations of different applications on a same computation architecture can be migrated to software during design time. However, the underlying GF(2m) arithmetic architecture needs to be designed with software programmability (or reconfigurability) in mind. We describe novel reconfigurable subword parallel GF(2m) arithmetic architectures designed with an associated instruction set architecture for different applications over GF(2m) and same applications with differing parameters. Design space exploration is carried out with two simple parameters P and Q which can be changed at design time and will affect the performance of different applications and flexibility of the final implementation. We show implementation results given for an FPGA prototype of the processor and programmed for RS and BCH coding, AES and elliptic curve cryptography with differing parameters. Complexity figures and configuration overheads for subword parallel GF(2m) arithmetic architectures are also estimated and discussed.