Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Instruction set extensions for software defined radio on a multithreaded processor
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme
IEEE Transactions on Computers
Instruction set extensions for software defined radio
Microprocessors & Microsystems
A universal VLSI architecture for Reed-Solomon error-and-erasure decoders
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Reed-Solomon (RS) coders are used for error-control coding in many applications such as digital audio, digital TV, software radio, CD players, and wireless and satellite communications. Traditionally, RS coders have been implemented using dedicated hardware. This paper considers software-based implementation of RS codecs. A hardware-software codesign approach is used to design the finite field datapath in a domain-specific digital signal processor (DSP) with low-energy RS codecs application in mind. These datapaths are designed to accommodate programmability with respect to the primitive polynomial as well as the field degree m. A novel heterogeneous digit-serial approach is proposed, where the heterogeneity corresponds to the use of different digit sizes in the multiply-accumulate (MAC) and degree reduction (DEGRED) subarrays. The salient feature of this digit-serial approach is that only the digit cells are implemented in hardware and the finite field multiplications are performed digit-serially in software by dynamically scheduling the internal digit-level operations. Efficient scheduling strategies for digit-serial finite field multiplications are presented and applied to the design of low-energy high-performance RS codecs in software. Significant energy and energy-latency reductions can be achieved using the digit-serial datapaths, as compared with the traditional approach where a combined MAC-DEGRED (parallel multiplier) unit is used. It is concluded that for two-error-correcting RS(n, k) codes over finite field GF(2/sup 8/), datapath containing a parallel MAC unit (of digit size eight) and a DEGRED unit with digit size two (or four) leads to RS codecs with the least energy consumption and energy-latency products; with these datapath architectures and appropriate digit-serial scheduling strategies, more than 60% energy reduction and more than one-third energy-latency reduction can be achieved compared with the parallel multiplication datapath-based approach.