A universal VLSI architecture for Reed-Solomon error-and-erasure decoders

Authors:
Hsie-Chia Chang;Chien-Ching Lin;Fu-Ke Chang;Chen-Yi Lee
Affiliations:
Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan;Ambarella Taiwan Ltd., Hsinchu, Taiwan and Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan;HIMAX Technologies, Inc., Hsinchu, Taiwan and Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan;Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2009

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Abstract

This paper presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers in the universal syndrome calculator and Chien search block, as well as an on-the-fly inversion table for calculating error or errata values. After implemented with 0.18-µm 1P6M technology, the proposed universal RS decoder correcting up to 16 errors can be measured to reach a maximum 1.28 Gb/s data rate at 160 MHz. The total gates count is around 46.4 K with 1.21 mm2 silicon area, and the average core power consumption is 68.1 mW.