Error control systems for digital communication and storage
Error control systems for digital communication and storage
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DSL: Simulation Techniques and Standards Development for Digital Subscriber Lines
DSL: Simulation Techniques and Standards Development for Digital Subscriber Lines
Reed-Solomon Codes and Their Applications
Reed-Solomon Codes and Their Applications
ADSL/Vdsl Principles: A Practical and Precise Study of Asymmetric Digital Subscriber Lines and Very High Speed Digital Subscriber Lines
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
High-speed VLSI architecture for parallel Reed-Solomon decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast parallel reed-solomon decoder on a reconfigurable architecture
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design of application-specific instructions and hardware accelerator for reed-solomon codecs
EURASIP Journal on Applied Signal Processing
A software defined approach for common baseband processing
Journal of Systems Architecture: the EUROMICRO Journal
A universal VLSI architecture for Reed-Solomon error-and-erasure decoders
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Reed-Solomon codec for a reconfigurable baseband processing platform
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
IEEE Transactions on Circuits and Systems Part I: Regular Papers
New Cost-Effective Simplified Euclid's Algorithm for Reed-Solomon Decoders
Journal of Signal Processing Systems
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Reed-Solomon (RS) codes play an important role in providing the error correction and the data integrity in various communication/storage applications. For high-speed applications, most RS decoders are implemented as dedicated application-specified integrated circuits (ASICs) based on parallel architectures, which can deliver high data throughput rate. For lower-speed applications, the RS decoding operations are usually performed by using fine-grained processing elements (PE) controlled by a programmable digital signal processing (DSP) core, which provides high flexibility. In this paper, we propose a novel m-PE multi-symbol-sliced (MSS) RS datapath structure. The -PE RS architecture is a highly scalable design and can be dynamically reconfigured at 1-PE, 2-PE,..., m/2-PE, and m-PE modes to deliver necessary data throughput rate. With the help of the gated-clock scheme to turn off the idle PEs, the proposed runtime configurable ASIC design provides good tradeoff between the data throughput rate and the power consumption. Hence, it can save energy to extend the battery life of the portable devices. We demonstrate a prototyping design using 4 PEs by using UMC 0.18-µm CMOS technology. The design can be dynamically reconfigured to be operated at 1-PE, 2-PE, and 4-PE modes, with performance of 140 Mb/s at 18.91 mW, 280 Mb/s at 28.77 mW, and 560 Mb/s at 48.47 mW, respectively. Compared with existing RS designs, the proposed -PE RS decoder has better normalized area/power efficiency than most DSP-type and ASIC-type RS designs. The reconfigurable feature makes our design a good candidate for the error control coding (ECC) unit of the storage system in power-aware portable devices.