On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays
IEEE Transactions on Computers
Error-control coding for computer systems
Error-control coding for computer systems
High-speed architectures for Reed-Solomon decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reed-Solomon Codes and Their Applications
Reed-Solomon Codes and Their Applications
A VLSI Design of a Pipeline Reed-Solomon Decoder
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New degree computationless modified euclid algorithm and architecture for reed-solomon decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high speed Reed-Solomon decoder
IEEE Transactions on Consumer Electronics
Architecture for decoding adaptive Reed-Solomon codes with variable block length
IEEE Transactions on Consumer Electronics
IEEE Transactions on Circuits and Systems for Video Technology
| Hi-index | 0.00 |
This paper proposes a cost-effective simplified Euclid's (SE) algorithm for Reed-Solomon decoders, which can replace the existing modified Euclid's (ME) algorithm. The new proposed SE algorithm, using new initial conditions and polynomials, can significantly reduce the computation complexity compared with the existing ME and reformulated inversionless Berlekamp-Massey (RiBM) algorithms, since it has the least number of coefficients in the new initial conditions. Thus, the proposed SE architecture, consisting of only 3t basic cells, has the smallest area among the existing key solver blocks, where t means the error correction capability. In addition, the SE architecture requires only the latency of 2t clock cycles to solve the key equation without initial latency. The proposed RS decoder has been synthesized using the 0.18 μm Samsung cell library, and the gate count of the RS decoder, excluding FIFO memory, is only 40,136 for the (255, 239, 8) RS code.