Error control systems for digital communication and storage
Error control systems for digital communication and storage
Applied coding and information theory for engineers
Applied coding and information theory for engineers
An area-efficient VLSI architecture of a Reed-Solomon decoder/encoder for digital VCRs
IEEE Transactions on Consumer Electronics
On the high-speed VLSI implementation of errors-and-erasures correcting reed-solomon decoders
Proceedings of the 12th ACM Great Lakes symposium on VLSI
New Systolic Architectures for Inversion and Division in GF(2^m)
IEEE Transactions on Computers
VLSI architecture of modified Euclidean algorithm for Reed-Solomon code
Information Sciences: an International Journal
Universal Reed-Solomon decoders based on the Berlekamp-Massey algorithm
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Reconfigurable adaptive FEC system with interleaving
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Design of application-specific instructions and hardware accelerator for reed-solomon codecs
EURASIP Journal on Applied Signal Processing
A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme
IEEE Transactions on Computers
An Improved Double Byte Error Correcting Code Using Cellular Automata
ACRI '08 Proceedings of the 8th international conference on Cellular Automata for Reseach and Industry
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Area-efficient Reed-Solomon decoder design for optical communications
IEEE Transactions on Circuits and Systems II: Express Briefs
Modified Euclidean algorithms for decoding Reed-Solomon codes
ISIT'09 Proceedings of the 2009 IEEE international conference on Symposium on Information Theory - Volume 2
A reconfigurable FEC system based on Reed-Solomon codec for DVB and 802.16 network
WSEAS Transactions on Circuits and Systems
Reed-Solomon codec for a reconfigurable baseband processing platform
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
Design of energy-efficient high-speed links via forward error correction
IEEE Transactions on Circuits and Systems II: Express Briefs
New architectural design of CA-based codec
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI implementation of BCH error correction for multilevel cell NAND flash memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-speed architecture for three-parallel Reed-Solomon decoder using S-DCME
Proceedings of the 4th International Conference on Uniquitous Information Management and Communication
Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications
Journal of Signal Processing Systems
Improving System Energy Efficiency with Memory Rank Subsetting
ACM Transactions on Architecture and Code Optimization (TACO)
PUFKY: a fully functional PUF-based cryptographic key generator
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
New Cost-Effective Simplified Euclid's Algorithm for Reed-Solomon Decoders
Journal of Signal Processing Systems
Nonlinear multi-error correction codes for reliable MLC NAND flash memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Unified architecture for Reed-Solomon decoder combined with burst-error correction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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New high-speed VLSI architectures for decoding Reed-Solomon codes with the Berlekamp-Massey algorithm are presented in this paper. The speed bottleneck in the Berlekamp-Massey algorighm is in the iterative computation of discrepencies followed by the updating of the error-locator polynomial. This bottleneck is eliminated via a series of algorithmic transformations that result in a fully systolic architecture in which a single array of processors computes both the error-locator and the error-evaluator polynomials. In contrast to conventional Berlekamp-Massey architectures in which the critical path passes through two multipliers and 1+[log2(t +1)] adders, the critical path in the proposed architecture passes through only one multiplier and one adder, which is comparable to the critical path in architectures based on the extended Euclidean algorithm. More interestingly, the proposed architecture requires approximately 25% fewer multipliers and a simpler control structure than the architectures based on the popular extended Euclidean algorithm. For block-interleaved Reed-Solomon codes, embedding the interleaver memory into the decoder results in a further reduction of the critical path delay to just one XOR gate and one multiplexer, leading to speed ups of as much as an order of magnitude over conventional architectures.