On the high-speed VLSI implementation of errors-and-erasures correcting reed-solomon decoders

Authors:
Tong Zhang;Keshab K. Parhi
Affiliations:
University of Minnesota;University of Minnesota
Venue:
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Year:
2002

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Abstract

Recently a novel algorithm transformation was proposed to reduce the critical path of Berlekamp-Massey algorithm implementation for errors-alone Reed-Solomon decoding. In this paper, we apply the same methodology to transform the Berlekamp-Massey algorithm for errors-and-erasures RS decoding. We present a regular hardware architecture to implement the reformulated Berlekamp-Massey algorithm, which can achieve high throughput. Moreover, an operation scheduling scheme is proposed to further reduce the hardware complexity without loss of throughput.