Unified architecture for Reed-Solomon decoder combined with burst-error correction

Authors:
Li Li;Bo Yuan;Zhongfeng Wang;Jin Sha;Hongbing Pan;Weishan Zheng
Affiliations:
Institute of VLSI Design, Nanjing University, Nanjing, China;Institute of VLSI Design, Nanjing University, Nanjing, China;Broadcom Corporation, Irvine, CA;Institute of VLSI Design, Nanjing University, Nanjing, China;Institute of VLSI Design, Nanjing University, Nanjing, China;Institute of VLSI Design, Nanjing University, Nanjing, China
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

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Abstract

Reed-Solomon (RS) codes are widely used as forward correction codes (FEC) in digital communication and storage systems. Correcting random errors of RS codes have been extensively studied in both academia and industry. However, for burst-error correction, the research is still quite limited due to its ultra high computation complexity. In this brief, starting from a recent theoretical work, a low-complexity reformulated inversion-less burst-error correcting (RiBC) algorithm is developed for practical applications. Then, based on the proposed algorithm, a unified VLSI architecture that is capable of correcting burst errors, as well as random errors and erasures, is firstly presented for multi-mode decoding requirements. This new architecture is denoted as unified hybrid decoding (UHD) architecture. It will be shown that, being the first RS decoder owning enhanced burst-error correcting capability, it can achieve significantly improved error correcting capability than traditional hard-decision decoding (HDD) design.