Decoding of Reed Solomon codes beyond the error-correction bound
Journal of Complexity
An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders
Journal of VLSI Signal Processing Systems
Fast factorization architecture in soft-decision Reed-Solomon decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved decoding of Reed-Solomon and algebraic-geometry codes
IEEE Transactions on Information Theory
Efficient decoding of Reed-Solomon codes beyond half the minimum distance
IEEE Transactions on Information Theory
Algebraic soft-decision decoding of Reed-Solomon codes
IEEE Transactions on Information Theory
High-throughput interpolation architecture for algebraic soft-decision Reed-Solomon decoding
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Backward interpolation architecture for algebraic soft-decision reed-solomon decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modified Low-Complexity Chase Soft-Decision Decoder of Reed---Solomon Codes
Journal of Signal Processing Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Unified architecture for Reed-Solomon decoder combined with burst-error correction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Algebraic soft-decision decoding of Reed-Solomon (RS) codes delivers promising coding gains over conventional hard-decision decoding. The most computationally demanding step in soft-decision decoding of RS codes is bivariate polynomial interpolation. In this paper, we present a hybrid data format-based interpolation architecture that is well suited for high-speed implementation of the soft-decision decoders. It will be shown that this architecture is highly scalable and can be extensively pipelined. It also enables maximum overlap in time for computations at adjacent iterations. It is estimated that the proposed architecture can achieve significantly higher throughput than conventional designs with equivalent or lower hardware complexity.