An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding

Authors:
Warren J. Gross;Frank R. Kschischang;P. Glenn Gulak
Affiliations:
McGill University, Montreal, Canada;University of Toronto, Canada;University of Toronto, Canada
Venue:
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2004

Citing 0
Cited 2

High-speed interpolation architecture for soft-decision decoding of Reed-Solomon codes

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Low-latency factorization architecture for algebraic soft-decision decoding of Reed-Solomon codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

We propose a parallel architecture for implementing the interpolation step in the Koetter-Vardy soft-decision Reed-Solomon decoding algorithm. The key feature is the embedding of both a binary tree and a linear array into a two-dimensional array processor, enabling fast polynomial evaluation operations. An FPGA interpolation processor was implemented and demonstrated at a clock frequency of 23 MHz, corresponding to decoding rates of 10-15 Mbps.