Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders

Authors:
Warren J. Gross;Frank R. Kschischang;Ralf Koetter;P. Glenn Gulak
Affiliations:
Department of Electrical and Computer Engineering, McGill University, 3480 University Street, Montreal, Quebec, H3A 2A7, Canada;Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, Toronto, Ontario, M5S 3G4, Canada;Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL, 61801, USA;Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, Toronto, Ontario, M5S 3G4, Canada
Venue:
Journal of VLSI Signal Processing Systems
Year:
2005

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Abstract

The Koetter-Vardy algorithm is an algebraic soft-decision decoder for Reed-Solomon codes which is based on the Guruswami-Sudan list decoder. There are three main steps: (1) multiplicity calculation, (2) interpolation and (3) root finding. The Koetter-Vardy algorithm seems challenging to implement due to the high cost of interpolation. Motivated by a VLSI implementation viewpoint we propose an improvement to the interpolation algorithm that uses a transformation of the received word to reduce the number of iterations. We show how to reduce the memory requirements and give an efficient VLSI implementation for the Hasse derivative.