Architecture and implementation of an interpolation processor for soft-decision Reed-Solomon decoding

Authors:
Warren J. Gross;Frank R. Kschischang;P. Glenn Gulak
Affiliations:
Department of Electrical and Computer Engineering, McGill University, Montreal, QC, Canada;Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada;Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2007

Citing 8
Cited 3

VLSI array processors

VLSI array processors
On Implementing Large Binary Tree Architectures in VLSI and WSI

IEEE Transactions on Computers
The Art of Computer Programming Volumes 1-3 Boxed Set

The Art of Computer Programming Volumes 1-3 Boxed Set
Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders

Journal of VLSI Signal Processing Systems
Fast factorization architecture in soft-decision Reed-Solomon decoding

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved decoding of Reed-Solomon and algebraic-geometry codes

IEEE Transactions on Information Theory
Efficient decoding of Reed-Solomon codes beyond half the minimum distance

IEEE Transactions on Information Theory
Algebraic soft-decision decoding of Reed-Solomon codes

IEEE Transactions on Information Theory

Algebraic soft-decision decoding of Hermitian codes

IEEE Transactions on Information Theory
High-throughput interpolation architecture for algebraic soft-decision Reed-Solomon decoding

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Backward interpolation architecture for algebraic soft-decision reed-solomon decoding

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.06

Visualization

Abstract

Reed-Solomon codes are powerful error-correcting codes that can be found in many digital communications standards. Recently, there has been an interest in soft-decision decoding of Reed-Solomon codes, incorporating reliability information from the channel into the decoding process. The Koetter-Vardy algorithm is a soft-decision decoding algorithm for Reed-Solomon codes which can provide several dB of gain over traditional hard-decision decoders. The algorithm consists of a soft-decision front end to the interpolation-based Guruswami-Sudan list decoder. The main computational task in the algorithm is a weighted interpolation of a bivariate polynomial. We propose a parallel architecture for the hardware implementation of bivariate interpolation for soft-decision decoding. The key feature is the embedding of both a binary tree and a linear array into a 2-D array processor, enabling fast polynomial evaluation operations. An field-programmable gate array interpolation processor was implemented and demonstrated at a clock frequency of 23 MHz, corresponding to decoding rates of 10-15 Mb/s.