Efficient embeddings of binary trees in VLSI arrays
IEEE Transactions on Computers
Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance
IEEE Transactions on Computers
Introduction to VLSI Systems
A VLSI tree machine for relational data bases
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Bounds on minimax edge length for complete binary trees
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
A model of computation for VLSI with related complexity results
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Optimal VLSI Dictionary Machines Without Compress Instructions
IEEE Transactions on Computers
A Modular Fault-Tolerant Binary Tree Architecture with Short Links
IEEE Transactions on Computers
An Efficient Dictionary Machine Using Hexagonal Processor Arrays
IEEE Transactions on Parallel and Distributed Systems
Utilizing spares in multichip modules for the dual function of fault coverage and fault diagnosis
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The authors present an efficient scheme for the layout of large binary-tree architectures by embedding the complete binary tree in a two-dimensional array of processing elements. Their scheme utilizes virtually 100% of the processing elements in the array as computing elements; it also shows substantial improvements in propagation delay and maximum edge length over H-tree layouts. They shown that their layouts readily lend themselves to fault-tolerant designs for overcoming fabrication defects in large-area and wafer-scale implementations of binary-tree architectures.