Introduction to VLSI Systems
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Computational Aspects of VLSI
A Generalized Dictionary Machine for VLSI
IEEE Transactions on Computers
The Binary Tree as an Interconnection Network: Applications to Multiprocessor Systems and VLSI
IEEE Transactions on Computers
Fault Tolerance in Binary Tree Architectures
IEEE Transactions on Computers
A Graph Model for Fault-Tolerant Computing Systems
IEEE Transactions on Computers
The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors
IEEE Transactions on Computers
Hypertree: A Multiprocessor Interconnection Topology
IEEE Transactions on Computers
A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures
IEEE Transactions on Computers - Fault-Tolerant Computing
On Implementing Large Binary Tree Architectures in VLSI and WSI
IEEE Transactions on Computers
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures
IEEE Transactions on Computers
Fuzzy primary representations of fuzzy ideals
Information Sciences: an International Journal
A Modular Fault-Tolerant Binary Tree Architecture with Short Links
IEEE Transactions on Computers
Design of a highly reliable cube-connected cycles architecture
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Bi-Level Reconfigurations of Fault Tolerant Arrays
IEEE Transactions on Computers
Reconfiguration Strategies for VLSI Processor Arrays and Trees Using a Modified Diogenes Approach
IEEE Transactions on Computers
A Cost-Effective Combining Structure for Large-Scale Shared-Memory Multiprocessors
IEEE Transactions on Computers
Design and Analysis of a Generalized Architecture for Reconfigurable m-ary Tree Structures
IEEE Transactions on Computers
IEEE Transactions on Computers
Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses
IEEE Transactions on Computers
IEEE Transactions on Computers
The Fault-Tolerant Extension Problem for Complete Multipartite Networks
IEEE Transactions on Parallel and Distributed Systems
Gracefully Degradable Pipeline Networks
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
An Augmented k-ary Tree Multiprocessor with Real-Time Fault-Tolerant Capability
The Journal of Supercomputing
| Hi-index | 15.02 |
An approach to the design of reconfigurable tree architectures is presented in which spare processors are allocated at the leaves. The approach is unique in that spares are associated with subtrees and sharing of spares between these subtrees can occur. The Subtree Oriented Fault Tolerance (SOFT) approach is more reliable than previous approaches capable of tolerating link and switch failures for both single-chip and multichip tree implementations while reducing redundancy in terms of both spare processors and links. VLSI layout is O(n) for binary trees and is directly extensible to N-ary trees and fault tolerance through performance degradation.