Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance
IEEE Transactions on Computers
Large-Capacity High-Throughput Low-Cost Pipelined CAM Using Pipelined CTAM
IEEE Transactions on Computers
An Efficient Implementation of Search Trees on [lg N + 1] Processors
IEEE Transactions on Computers
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We show that a machine in which the processors are interconnected as a binary tree can support all the dictionary and priority queue operations as well as some other data queries. Every one of the operations takes O(log n) steps where n is the number of keys present. A sequence of operations can be pipe-lined at a constant rate. In previous designs, either an operation required O(log N) steps where N is the total capacity of the machine, i.e., the maximum number of keys that can be stored in it, or O(log n) performance was achieved at the expense of additional wires.