Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance
IEEE Transactions on Computers
A fault tolerant massively parallel processing architecture
Journal of Parallel and Distributed Computing
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures
IEEE Transactions on Computers
Designing fault-tolerant systems using automorphisms
Journal of Parallel and Distributed Computing
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Programming real-time multicomputers for signal processing
Programming real-time multicomputers for signal processing
Tolerating faults in a mesh with a row of spare nodes
Theoretical Computer Science - Special issue on dependable parallel computing
Fault-Tolerant Meshes and Hypercubes with Minimal Numbers of Spares
IEEE Transactions on Computers
Fault-Tolerant de Bruijn and Shuffle-Exchange Networks
IEEE Transactions on Parallel and Distributed Systems
Fault Tolerance in Binary Tree Architectures
IEEE Transactions on Computers
A Graph Model for Fault-Tolerant Computing Systems
IEEE Transactions on Computers
The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors
IEEE Transactions on Computers
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A pipeline is a linear array of processors with an input node at one end and an output node at the other end. This paper presents k-gracefully-degradable graphs which, given any set of up to k faults, contain a pipeline that uses all the healthy processor nodes. Our constructions are designed to tolerate faulty input and output nodes, but they can be adapted to provide solutions when the input and output nodes are guaranteed to be healthy. All of our constructions are optimal in terms of the number of nodes and the maximum degree of the processor nodes.