Distributed Recovery in Fault-Tolerant Multiprocessor Networks
IEEE Transactions on Computers
Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance
IEEE Transactions on Computers
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Dynamically reconfigurable optimal fault-tolerant structures of hierarchical tree systems
Dynamically reconfigurable optimal fault-tolerant structures of hierarchical tree systems
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Design and Analysis of a Generalized Architecture for Reconfigurable m-ary Tree Structures
IEEE Transactions on Computers
IEEE Transactions on Computers
Fault-tolerant meshes with small degree
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
Construction of the mesh and the torus tolerating a large number of faults
SPAA '94 Proceedings of the sixth annual ACM symposium on Parallel algorithms and architectures
Node-covering, Error-correcting Codes and Multiprocessors with Very High Average Fault Tolerance
IEEE Transactions on Computers
Fault-Free Hamiltonian Cycles in Faulty Arrangement Graphs
IEEE Transactions on Parallel and Distributed Systems
Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring
IEEE Transactions on Computers
Computing in the RAIN: A Reliable Array of Independent Nodes
IEEE Transactions on Parallel and Distributed Systems
Fault-Tolerant Meshes and Hypercubes with Minimal Numbers of Spares
IEEE Transactions on Computers
Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy
IEEE Transactions on Computers
Fault-Tolerant de Bruijn and Shuffle-Exchange Networks
IEEE Transactions on Parallel and Distributed Systems
Survivable Computer Networks in the Presence of Partitioning
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Gracefully Degradable Pipeline Networks
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
What Designers of Bus and Network Architectures Should Know about Hypercubes
IEEE Transactions on Computers
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Tolerant Switched Local Area Networks
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
An Augmented k-ary Tree Multiprocessor with Real-Time Fault-Tolerant Capability
The Journal of Supercomputing
A Proxy-Network Based Overlay Topology Resistant to DoS Attacks and Partitioning
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 16 - Volume 17
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A general approach to designing tree structured multiprocessors with optimal or near-optimal fault tolerance properties is developed. A multiprocessor architecture with a static interconnection network is represented by a graph whose nodes are processors and whose edges are interprocessor communication links. The design of k-fault-tolerant (FT) trees for arbitrary k is considered, with the primary goal of minimizing the number of spare nodes and edges. Also presented are strategies for reconfiguring a k-FT supergraph of a tree T around faults to obtain a fault-free tree isomorphic to T. A systematic methodology is presented for designing k-FT nonhomogeneous symmetry d-ary trees based on a concept termed node covering. The designs are shown to be optimal when kd and near-optimal otherwise. It is also shown that these k-FT designs can be implemented efficiently using switches to share redundant links.