Configuration of VLSI Arrays in the Presence of Defects
Journal of the ACM (JACM)
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
IEEE Transactions on Computers
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures
IEEE Transactions on Computers
Designing fault-tolerant systems using automorphisms
Journal of Parallel and Distributed Computing
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors
IEEE Transactions on Computers - Special issue on fault-tolerant computing
The Connection Network Class for Fault Tolerant Meshes
IEEE Transactions on Computers
Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses
IEEE Transactions on Computers
A Cube-Connected Cycles Architecture with High Reliability and Improved Performance
IEEE Transactions on Computers
Fault-Tolerant Meshes and Hypercubes with Minimal Numbers of Spares
IEEE Transactions on Computers
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Totally defect-tolerant arrays capable of quick broadcasting
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Fault-Tolerant Shuffle-Exchange and de Bruijn Networks Capable of Quick Broadcasting
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Enhanced Cluster k-Ary n-Cube, A Fault-Tolerant Multiprocessor
IEEE Transactions on Computers
An efficient reconfiguration scheme for fault-tolerant meshes
Information Sciences—Informatics and Computer Science: An International Journal
An improved replacement algorithm in fault-tolerant meshes
Proceedings of the 2007 Summer Computer Simulation Conference
An efficient reconfiguration scheme for fault-tolerant meshes
Information Sciences: an International Journal
Ubiquitous evolvable hardware system for heart disease diagnosis applications
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
An evolvable hardware system under uneven environment
KES'05 Proceedings of the 9th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part II
The survivability of design-specific spare placement in FPGA architectures with high defect rates
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hi-index | 14.98 |
An advanced spare-connection scheme for k-out-of-n redundancy called 驴generalized additional bypass linking驴 is proposed for constructing fault-tolerant massively parallel computers with series-connected, mesh-connected, or tree-connected processing element (PE) arrays. This scheme uses bypass links with wired OR connections to selectively connect the primary PEs to a spare PE in parallel. These bypass links are allocated to the primary PEs by node-coloring of a graph with a minimum inter-node distance of three in order to minimize the number of bypass links (i.e., the chromatic number). The main advantage of this scheme is that it can be used for constructing various k-out-of-n configurations capable of enhanced PE-to-PE communication and broadcast while still achieving strong fault tolerance for these PEs and links. In particular, it enables the construction of optimal r-strongly-fault-tolerant configurations capable of direct k-out-of-n selections by providing r spare PEs and $r$ extra connections per PE for any kind of array when node-coloring with a distance of three is used. This simple spare-circuit structure enhances fault tolerance more than conventional schemes do. The node-coloring patterns were constructed using new node-coloring algorithms and the chromatic numbers were evaluated theoretically. Enhanced PE-to-PE communication and broadcast were achieved by using new fault-tolerant routing algorithms based on the properties of the node-coloring patterns with four or five message transmission steps being optimal configurations with any size array.