Face Recognition by Elastic Bunch Graph Matching
IEEE Transactions on Pattern Analysis and Machine Intelligence
A reconfigurable arithmetic array for multimedia applications
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Proceedings of the First International Conference on Evolvable Systems: From Biology to Hardware
ICES '96 Proceedings of the First International Conference on Evolvable Systems: From Biology to Hardware
Modeling and mapping for dynamically reconfigurable hybrid architectures
Modeling and mapping for dynamically reconfigurable hybrid architectures
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This paper proposes an evolvable hardware system with capability of evolution under uneven image environment, which is implemented on reconfigurable field programmable gate array (FPGA) platform with ARM core and genetic algorithm processor (GAP). Parallel genetic algorithm based reconfigurable architecture system evolves image filter blocks to explore optimal configuration of filter combination, associated parameters, and structure of feature space adaptively to uneven illumination and noisy environments for an adaptive image processing. The proposed evolvable hardware system for image processing consists of the reconfigurable hardware module and the evolvable software module, which are implemented using SoC platform board with the Xilinx Virtex2 FPGA, the ARM core and the GAP. The experiment result shows that images affected by various environment changes are enhanced for various illumination and salt & pepper noise image environments.