Reconfigurable VLSI architectures for evolvable hardware: from experimental field programmable transistor arrays to evolution-oriented chips

  • Authors:

  • Ricardo Zebulum;Didier Keymeulen;Raoul Tawel;Taher Daud;Anil Thakoor;Adrian Stoica

  • Affiliations:

  • Jet Propulsion Lab., California Institute of Technology, Pasadena, CA;Jet Propulsion Lab., California Institute of Technology, Pasadena, CA;Jet Propulsion Lab., California Institute of Technology, Pasadena, CA;Jet Propulsion Lab., California Institute of Technology, Pasadena, CA;Jet Propulsion Lab., California Institute of Technology, Pasadena, CA;Jet Propulsion Lab., California Institute of Technology, Pasadena, CA

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
  • Year:
  • 2001

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Abstract

Evolvable hardware (EHW) addresses on-chip adaptation and self-configuration through evolutionary algorithms. Current programmable devices, in particular the analog ones, lack evolution-oriented characteristics. This paper proposes an evolution-oriented field programmable transistor array (FPTA), reconfigurable at transistor level. The FPTA allows evolutionary experiments with reconfiguration at various levels of granularity. Experiments in SPICE simulations and directly on a reconfigurable FPTA chip demonstrate how the evolutionary approach can be used to automatically synthesize a variety of analog and digital circuits.